This invention relates to a digital to analog converter for converting a multibit digital input signal into an analog output signal, the converter comprising a set of substantially equal conversion elements of one polarity and conversion element selection logic for selecting, in response to the multibit digital input signal, from said set of conversion elements a number of signal-conversion elements for connection to an output terminal, the selection logic being adapted to perform a dynamic element matching algorithm. A digital to analog converter of this kind is e.g. known from the article: xe2x80x9cLinearity Enhancement of Multibit Delta Sigma A/D and D/A Converters Using Data Weighted Averagingxe2x80x9d by R. T. Baird and T. S. Fiez in IEEE Transactions on Circuits and Systems-II: analog and digital signal processing, Vol. 42, No. 12, pp. 753-762, December 1995.
In audio and instrumentation applications, where low-frequency, high-resolution and high-linearity conversion is required, oversampling and noise-shaping AID and D/A converters have displaced the traditional architectures. In these converters, single-bit A/D and D/A converters can be used which inherently have an extremely good linearity. This inherent linearity makes these converters very suitable for implementation in modern IC processes, as these processes generally tend to be optimized for high-frequency devices, but have relatively large component variations and matching tolerances.
Although the quantization noise that is produced by single-bit converters is placed outside the frequency band of interest by these oversampling and noise-shaping converters, the total amount of quantization noise is very large, as only one bit is used in the conversion. In converters where an extremely high-resolution conversion is required, such as geoseismic measurements or high-resolution audio, the quantization noise produced by these single-bit converters can be too large. Also, in converters for very large bandwidths, such as converters for video signals, the quantization noise produced by these single-bit converters can be too large, as the oversampling ratio in this type of converter is limited, due to the relatively large bandwidth of the input signal. Moreover, very often the out-of-band quantization noise has to be removed before the signal can be processed by the following electronic circuitry or actuator. When the amount of out-of-band quantization noise is very large, the analog filters that are required for this operation can be very power consuming and very expensive in silicon area.
In these cases, the use of multibit converters is preferred over single-bit converters. The quantization-noise level of the multibit quantizers is inherently lower than that of single-bit quantizers (the theoretical signal to noise ratio of the system improves by approximately 6 dB per bit). Moreover, multibit converters also have the advantage of being less sensitive to sample-clock jitter and intersymbol interference.
The improvement of the dynamic range of multibit converters however only comes at the cost of severe linearity problems. When the value of the conversion elements is not exactly equal, the quantization levels are not exactly equidistant, the converter is nonlinear and severe harmonic distortion in the output signal is generated.
It is well known in the art, e.g. from the U.S. Pat. Nos. 3,982,172 and 4.703.310 of R. J. van de Plassche, to improve the linearity of multibit converters by techniques of dynamic element matching. These techniques do not rely on analog accuracies and are therefore often preferred in modern IC processes. Although, of course, for converting a certain value of the digital input signal, the corresponding number of conversion elements is selected, the technique of dynamic element matching seeks to avoid that for each conversion, the same conversion elements are selected. Therefore dynamic element matching decorrelates the mismatch errors of the conversion elements from the input signal, thereby reducing non-linear distortion, i.e. the generation of higher harmonics in the analog output signal. Some special kinds of dynamic element matching do not only decorrelate the mismatch errors from the input signal, but additionally xe2x80x9cshapexe2x80x9d the noise, caused by the inequalities of the conversion elements, out of the frequency band of interest. A simple and preferred method of dynamic element matching, belonging to this latter category, is the Data Weighted Averaging (DWA) algorithm, which is described in the above referenced article. In this algorithm, for each conversion the next K unit elements are used, K being the number of elements to be selected. In this way, the error that is caused by the mismatch is averaged as fast as possible, and thus the mismatch error becomes a high-frequency error by first-order shaping.
When both the converter""s quantization noise is reduced by the use of multibit input signal and the linearity errors are minimized by the use of dynamic element matching, the noise of the electronic components is often dominant. The present invention has for its object to provide a digital to analog converter which is, compared with the above referenced article, in this respect improved and the digital to analog converter of the present invention is therefore characterized in that the converter further comprises a second set of substantially equal opposite-polarity conversion elements for output-signal excursions which are opposite to the output-signal excursions obtained by the first mentioned set of conversion elements and second conversion-element selection logic for selecting, in response to the multibit digital input signal, from said second set of conversion elements a second number of signal-conversion elements for connection to the said output terminal, the second selection logic being also adapted to perform a dynamic element matching algorithm. The noise reduction of this converter is mainly based on the following: when the converter has to deliver a value close to xe2x80x9czeroxe2x80x9d, no or only few elements are selected in each of the two sets to deliver the analog output. As the contribution of the selected elements is relatively small, as compared to the full-scale output signal, the noise at the output of this converter can be much smaller. Therefore, the dynamic range of such a converter can be much larger than that of many other converters.
It may be observed, that dual-set digital to analog converters are known per se e.g. from U.S. Pat. No. 5,689,259. The digital to analog converter shown in this document does, however, neither show the use of a dynamic element matching algorithm, nor the use of substantially equal selectable conversion elements.
With the above described digital to analog converter, with two sets of conversion elements, one for the positive signal excursions and one for the negative signal excursions, the shaping of the linearity errors by the dynamic element matching algorithm appears to be less efficient than with a converter of only one set of conversion elements for both the positive and the negative signal excursions. This is caused by the fact that the dynamic element matching algorithm that is applied to the xe2x80x9cpositivexe2x80x9d set of elements stops when a negative signal excursion is made, because no elements of this set of elements are selected for contributing to the output signal and equally that the dynamic element matching algorithm for the xe2x80x9cnegativexe2x80x9d set of elements stops when a positive signal excursion is made. When a dynamic element matching algorithm temporarily stops, a larger period of time elapses between the mismatch errors, with the result that the algorithm can no longer shape the mismatch errors to higher frequencies and that low-frequency errors now appear as a noisy signal within the frequency band of interest. It is a further object of the invention to avoid these low-frequency errors in dual conversion-set converters and the digital to analog converter of the present invention may be further characterized in that the first mentioned selection logic additionally selects, from said first mentioned set of conversion elements, a number of excess conversion elements for connection to the output terminal and that the second selection logic additionally selects, from the second set of conversion elements, an equal number of excess conversion elements for connection to the output terminal. Basically, the selection of excess conversion elements cause the dynamic element matching algorithms to continue their operation, thereby preventing the occurrence of low-frequency mismatch errors.
It has to be observed, that the number of excess conversion elements during positive signal excursions may be different from the number of excess conversion elements during negative signal excursions. It is even possible that the number of excess elements differ from sample to sample. However, in a preferred embodiment of this digital to analog converter, the number of excess conversion elements is constant and equal to 1 both during positive and during negative signal excursions. This choice enables good dynamic element matching and good thermal noise performance, as only few conversion elements are connected to the output of the converter when small signals have to be converted. When the number of excess elements is larger than 1, more noise is added to the output. However in some cases it can be favourable for the performance of the dynamic element matching algorithm to choose the number of excess conversion elements to be larger than 1.
In the present application, the term xe2x80x9csignal-conversion elementxe2x80x9d is used to identify those conversion elements, which are selected to constitute the analog output signal, in contradistinction to the xe2x80x9cexcess conversion elementsxe2x80x9d which are selected to avoid the temporary stops of the dynamic element matching algorithm.
In the dual-set digital to analog converter of the present invention positive signal excursions are made by the xe2x80x9cpositivexe2x80x9d set of conversion elements and negative excursions are made by the xe2x80x9cnegativexe2x80x9d set. When the average value of the conversion elements in one set is not exactly equal to the average value of the elements in the other set, the circuit is not symmetrical, resulting in even order harmonic distortion in the output signal. In the dual-set digital to analog converter wherein the mismatch errors caused by the differences in the conversion elements within one set are solved by the dynamic element matching algorithm, this additional problem may be solved in a digital to analog converter with a differential analog output without increasing the number of sets of elements and the digital to analog converter of the present invention may therefore be further characterized in that the first mentioned selection logic additionally controls the second set of conversion elements, whereby, simultaneously with the connection of the first mentioned number of signal-conversion elements from the first set to the first mentioned output terminal, an equal number of signal-conversion elements is selected from the second set of conversion elements for connection to the second output terminal and that the second selection logic additionally controls the first mentioned set of conversion elements, whereby, simultaneously with the connection of the second number of signal-conversion elements from the second set to the first mentioned output terminal, an equal number of signal-conversion elements from the first set is selected for connection to the second output terminal.
In this differential-output digital to analog converter, notwithstanding the fact that each set of conversion elements operates during both the positive and the negative signal excursions, the ineffectiveness of the dynamic element matching algorithms still exists, because the selection of signal-conversion elements towards a particular output terminal temporarily stops when the signal-conversion elements are selected for connection to the other output terminal. To overcome this problem the dual-set differential-output analog to digital converter of the present invention may be further characterized in that the first mentioned selection logic additionally selects, from said first mentioned set of conversion elements a first number of excess conversion elements for connection to the first mentioned output terminal, that the first mentioned selection logic additionally selects, from said second set of conversion elements a second number of excess conversion elements for connection to the second output terminal, that the second selection logic additionally selects, from said second set of conversion elements a third number of excess conversion elements for connection to the first mentioned output terminal, that the second selection logic additionally selects, from said first mentioned set of conversion elements a fourth number of excess conversion elements for connection to the second output terminal and that the sum of the first number of excess conversion elements and the second number of excess conversion elements is equal to the sum of the third number of excess conversion elements and the fourth number of excess conversion elements.
The dynamic element matching algorithms of the two selection logics run through the set of conversion elements with different velocities, which implies that from time to time both selection logics are scheduled to simultaneously select the same conversion element. This problem may e.g. be solved by causing one of the selection logics to shift its selection to the first next conversion element which is not selected by the other selection logic. However, such solution is a violation of the proper operation of the dynamic element matching algorithm, because a conversion element with the wrong error is selected and moreover it is difficult to implement. It is a still further object of the invention to overcome this problem in a simpler and better way and the digital to analog converter of the present invention is therefore characterized by means to compare the operation of the two selection logics with each other to identify any conversion element which is scheduled for simultaneous selection by both selection logics and to cancel the selection of such conversion element by each of the two selection logics.